From the course: Linux Performance Tuning
Join today to access over 22,500 courses taught by industry experts or purchase this course individually.
Page sizes and page faults - Linux Tutorial
From the course: Linux Performance Tuning
Page sizes and page faults
- [Instructor] When it comes to address translation, including page fault related stuff, we want to talk about the TLB again, the translation lookaside buffer. The TLB is a little cache in the CPU, that maps virtual addresses to physical addresses. And that's based on pages. The unit size for address translation is a page. A process is given a page at at time, and you get all of the bytes in that page at a time. So, TLB entries, you can think of as mapping pages to pages, physical and virtual page relationship. Different processors have different sized TLBs or different TLB architectures. For example, Intel's i7, has a two-level TLB. The first level has data and instruction. There are 64 entries for 4K pages or 32 entries if you're using large pages or huge pages, 2M or 4M pages. That's not a lot of entries, and newer processors tend to have bigger TLBs. Faster processors have bigger TLBs, but it could be significantly smaller than that. The level one has only 128 entries. The larger…
Download courses and learn on the go
Watch courses on your mobile device without an internet connection. Download courses using your iOS or Android LinkedIn Learning app.