From the course: Learning Verilog for FPGA Development
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A shift register example - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
A shift register example
- [Instructor] It's demo time. Let me show you a simple 8-bit shift register with parallel load, which only performs the shift left operation. The module is at the left. The code is quite simple. In the ports list, starting at line 24, we have an 8-bit data input for parallel load named Din, a parallel load triggering line, which is active low, the clock line, and the actual 8-bit register named D. The sensitivity to the falling edges of the clock and parallel load inputs starts at line 29. Whenever we have a value of zero in PL, the D register gets the value from the input Din. Now, the sequential part starts at line 33 where the shift is performed only if the parallel load line is inactive. The shift is what you would expect, a series of assignments among bits with a zero entering at the least significant bit. But notice that the order of these lines of code doesn't really matter, because what we mean with this code…
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