From the course: Learning Verilog for FPGA Development

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Stimulus variables

Stimulus variables - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Stimulus variables

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- Since a test bench module is a wrapper for the device under test. A test bench needs to have as many registers or variables as inputs in the DUT. And as many wires as outputs in it. So here's a test bench for a full adder. This is the same simulation I showed you earlier on instantiating modules. Remember that the full adder has three inputs and two outputs, all of them one bit long. That's why we have three registers, A, B, and C in line 24, and a two bit wire bus S in line 25. Now look at line 27. And take a minute to verify that the connections are correct in this instantiation. And finally notice the assignments at line 30 through 37. This is where the simulation is going on. I'm using the concatenation operator to assign a three bit value to the three registers, A, B, and C at once.

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