From the course: Learning Verilog for FPGA Development

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Solution: Make a clock divider

Solution: Make a clock divider - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Solution: Make a clock divider

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(upbeat music) - So how did you do? I must say that it got a bit tricky for me. So I added a couple of display lines to verify what was going on in my simulation. Let's get started. In line 29, we have the counter which is a 32 bit register. Then starting at line 31, we have the main always block, which is sensitive to the positive edge of the input clock and to the negative edge of the reset line. Then we have the reset logic at line 32. This is similar to what we saw with the shift register. When the reset line goes low, I reset the counter and the output to zero. Notice that this part inhibits the whole state machine because the reset line is low. If not, the module will act depending on the count. First, if the count has reached the ratio minus one, I reset the output and the count. This is where I added a display line for debugging. Keep in mind that calls to system tasks are not synthesizable. So…

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