From the course: Learning Verilog for FPGA Development

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Solution: Make a 4-bit arithmetic logic unit (ALU)

Solution: Make a 4-bit arithmetic logic unit (ALU) - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Solution: Make a 4-bit arithmetic logic unit (ALU)

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(upbeat music) - How did you do? I hope you didn't run into much trouble. Now let's look at my solution. Here's the ALU module. As you can see, it simply consists of a case statement in an always block. Looking at the cases, you'll see that all of the operations are implemented in the language. So they are all just one line long. You may want to take a minute to verify that these operators are correct. And now let's look at the test bench. As you can see, it has the usual definition of stimulus variables, and the DUT instantiation. To keep it simple I've reported all values with the monitor task in line 32. Now this line may not look so simple, but you may want to hit pause to verify that it's simply showing what A, operated with B results in. The long sequence of conditional operations, the ternary operator, is placing the right operator in the string. So when the operation is true, for example the percentage…

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