From the course: Learning Verilog for FPGA Development

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Solution: From schematic to code

Solution: From schematic to code - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Solution: From schematic to code

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(bouncy music) - [Instructor] Did you get it to work? Did you run into trouble? Either way, give yourself a pat on the back. You have accomplished so much. Let me show you my solution. Now, in order to show you the freedom you have in Verilog, I'll show you three implementations. The first one is a gate implementation, which I've named is_prime_gates. As you can see in the code, it consists of three intermediate wires and four gates. Notice that I've included where these wires, w1, w2, and w3 are located in the schematic. You may want to pause the video and take a minute to verify that the connections are correctly implemented. My second implementation uses a continuous assignment. We can find it under sources, and design sources. I've named this one is_prime_boolean. This is my favorite implementation because it uses just one line of code. The module is called is_prime_boolean because it's implemented with…

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