Learn about the structure and syntax used when creating a test bench module in Verilog.
- [Instructor] Let's take a look at some … of the basic elements of Verilog Simulation. … Simulations are specified by test bench modules. … And these modules must instantiate … whatever module you want to test out. … Your test bench is supposed to provide … input signals to that module under test. … And the simulation consists on running … the sequence of events you specify. … The behavior of your module under test, … will determine the results of this simulation. … Now, here we have a few pointers … on the syntax used in test bench modules in Verilog. … A test bench is not required to specify ports. … Because you're usually interested in running a sequence. … Providing your own values to the module under test. … You must separate events in time somehow. … For this, you can instruct the simulator … to wait for some time with the pound symbol. … For example, pound 10, means wait for 10 units of time. … These ten units could be nanoseconds, microseconds, … or any other duration you want. …
- What is an FPGA?
- FPGA use cases
- Logic blocks and interconnects
- The FPGA development process
- Reviewing the hardware description languages
- Running FPGA simulations
- Implementing an FPGA design
Skill Level Intermediate
Learning Arduino: Interfacing with Hardwarewith Zahraa Khalil1h 40m Intermediate
What you should know1m 9s
1. Field Programmable Gate Arrays
2. Embedded Development Process
3. Hardware Description Languages
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