From the course: Learning Verilog for FPGA Development
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Register-transfer level - FPGA Tutorial
From the course: Learning Verilog for FPGA Development
Register-transfer level
- [Instructor] At the register transfer level, or RTL, we are not so much interested in the exact gates that will implement our design. And this is a good thing because FPGAs don't usually provide a lot of gates for you. Instead, to implement arbitrary combinational logic, FPGAs have lookup tables which implement Boolean functions with a fixed number of inputs. This means that your design will be implemented with the best combination of elements the compiler can produce in order to behave as you want with the elements you specify. So the higher RTL level of abstraction is quite useful for FPGAs because you don't have to micromanage the design at the gate level. So for this schematic example, I've shown a half adder you may be familiar with. It's very simple. It consists of an and gate and an xor gate. So in Verilog, it takes two lines of code. One for each gate. Notice that the order of these lines is irrelevant…
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