From the course: Learning Verilog for FPGA Development

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Instantiating modules

Instantiating modules - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Instantiating modules

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- [Male] Instantiating a Verilog module is very similar to calling a constructor method, in an object oriented programming language. You simply declare a new element, with the module's name as it's type, and you need to specify the wires you want to connect to its ports. Now, for the port connections, you may simply specify the connections by ordered list, meaning in the order you specified when you wrote your module's code. You may be okay with this option, if you're used to writing code in C, or Java, like myself. However, Verilog also supports port connections by name. This is a very nice feature you may find in programming languages like Python, C#, or Kotlin. It consists in using the names of the ports when you instantiate, without having to rely on the order in their declaration, let me show you what I mean. At the left, we have the same full adder module we saw earlier, and at the right, we have the half adder,…

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