From the course: Learning Verilog for FPGA Development

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Initial and always blocks

Initial and always blocks - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Initial and always blocks

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- [Narrator] Now let me remind you about a very important detail of Verilog test bench modules. Everything works concurrently because we are describing hardware after all. Every line of code and every block of code work concurrently. This includes gates and module instances, registers and wires, but more importantly, all initial blocks work concurrently, so you may include several of these in a single module. Always blocks also operate concurrently with everything else. Yes, procedural blocks, the ones enclosed by begin and end, may have sequential parts, but this sequence only refers to the auditor of the assignments and delays expressed with the pound operator. So in any test bench module we could have several initial blocks, some module instantiations, then an always block, then more initial blocks and so on. The order of these blocks doesn't change the behavior of the simulation or the module. Again, the order…

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