From the course: Learning Verilog for FPGA Development

Hardware description languages - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Hardware description languages

- [Narrator] The first thing you need to remember is that hardware description languages are computer languages useful for describing digital circuits, not programs to be executed by a CPU. The two most widely used hardware description languages are Verilog and VHDL. So, what are hardware description languages, or HDLs, used for? Well, the purpose of an HDL is hardware entry, just like a schematic capture tool where you enter a circuit graphically by connecting gates with wires. Later, a simulator may interpret the hardware to predict its behavior. Or, a synthesis tool may implement the design in a field programmable gate array or FPGA, or even on an application specific integrated circuit or ASIC. These targets are both integrated circuits and the difference is that an FPGA is flexible so it may behave as whichever system you want while ASIC chips are rigid, implementing only one system. Now, the biggest difference between a hardware description language and a programming language is that HDL code is concurrent. To illustrate this, think of C, Java, or Python, where the lines of code mean instructions to be sequentially executed by a computer. On the other hand, Verilog and the HDL lines of code mean elements like gates and flip-flops in a circuit. This mean that there is no implicit order in an HDL piece of code because all of these gates work concurrently as hardware. Here you will see two pieces of code that may look alike but are very different. First, we have three lines of Java code which perform three logical operations to variables A through E, assigning the results to variables X, Y, and Z respectively. First X, then Y, and then Z. Each of these lines of code is evaluated once, each at its own turn. Always remember, this is software. Next, we have three lines of Verilog code which specify three logic gates that perform the same three operations to identifiers with the same names as in the Java code, but concurrently not sequentially. There is no concept of evaluating one gate before another because they are coexisting interconnected gates. Always remember, this is hardware. Now let me tell you some details about Verilog and the coding style you will see in this course. First, Verilog is formally standardized as IEEE 1364 and it has had three versions: Verilog 95, Verilog 2001, and Verilog 2005. You may still find a lot of Verilog 95 code today. Verilog 2001 added a lot of features to the language, so many features that compatibility with Verilog 95 may be a problem. Since we will be using Verilog 2001 in this course, please make sure your development software is using Verilog 2001 or later. Finally, you must be aware that Verilog is not the same thing as SystemVerilog, which is a hardware description and verification language. It's a superset of Verilog, so you may find SystemVerilog development tools that support Verilog just like C++ compilers support C.

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