From the course: Learning Verilog for FPGA Development

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Getting your clock divider on an FPGA

Getting your clock divider on an FPGA - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Getting your clock divider on an FPGA

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As a second bonus, let's see the clock divider working on a basis three board for this application will use the 100 megahertz signal generated by an onboard oscillator. This enormously fast signal is not visible to the human eye. so we'll slow it down to one hertz, so that we are finally able to see it blink once each second. Here's how we'll use the hardware. The 100 megahertz signal will be routed directly to the rightmost LED, that's led zero and the state of the one hertz signal will be shown in the rightmost digit of the segment display. That is to say, the display will show either a zero or one as digits. To show the clock divider working I only need two pins, a clock input and an LED output. However, since I'll use the segment display, I'll use some more pins just to make this exciting. So here we have the XDC file for the basis three board with lines: seven, eight and nine enabled. These lines enabled…

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