From the course: Learning Verilog for FPGA Development

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Display tasks

Display tasks - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Display tasks

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- [Instructor] Verilog supports two very convenient Display Tasks. These are display and monitor. The difference is very subtle. Display sends formatted text to the console output once while monitor sends the same text whenever any of the variables you are displaying changes. If you are familiar with the C programming language, you may be pleased to know that these tasks work pretty much like the printf family of functions. If not, don't worry. They simply output values to the console with a format specified by their first argument. The remaining arguments are the variables you want to display. Let me show you an example to illustrate these tasks. Here we have a standalone testbench module. Notice that I'm defining variables a and b as bit registers. So we'll assign values to them throughout the simulation. Now in line 28, we have the monitor call, where I'm displaying the value of a. Notice that the format string…

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