From the course: Learning Verilog for FPGA Development

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Challenge: Make a 4-bit arithmetic logic unit (ALU)

Challenge: Make a 4-bit arithmetic logic unit (ALU) - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Challenge: Make a 4-bit arithmetic logic unit (ALU)

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(upbeat electronic music) - It's time for another challenge, now you must write a Verilog module for a 4-bit arithmetic logic unit. Don't worry, it's just a fancy name for a combinational module that performs an operation on two numbers. This is the deceration line for the ALU. It has two inputs, A and B. Both, four bits long. It also has a 2-bit input to set the operation to perform, so it must support four operations. And finally, an 8-bit output. Why 8-bits? Well, because one operation is multiplication and we want to output the whole result. If you need the output to be a register, make the changes you need. So the operations you must implement are addition, multiplication, modulo, and bitwise AND. And this is how you are expected to implement these operation. When the operation input is zero, addition. One, Multiplication. Two, Modulo. And three, bitwise AND. For your implementation keep in mind,…

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