From the course: Learning Verilog for FPGA Development

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Challenge: From schematic to code

Challenge: From schematic to code - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Challenge: From schematic to code

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(upbeat music) - [Narrator] Now it's time to test your knowledge with a challenge. Your task is to write a Verilog module that implements this circuit. Just take the schematic and put it in a Verilog module. This circuit's output is a logical 1, or true, when the binary number formed by its inputs, c, b, and a, is a prime number. Consider c as the most significant bit, and a as the least significant bit. In other words, P is true whenever the input is two, three, five or seven and it's false for zero, one, four and six. For your implementation, keep in mind you may use gates, you may use an assign statement or your may use an always block. These are three different options you have, not requirements, so please don't try to combine them. And finally, please feel free to use the provided Vivado simulation project to test your code. In this project, I've already written the code for a simulation that takes your code…

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