From the course: Learning Verilog for FPGA Development

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Blocking assignments

Blocking assignments - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Blocking assignments

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- At this point, I've shown you procedural blocks using blocking assignments exclusively. It's time to learn what blocking and non-blocking means in Verilog. Consider this module called logic which outputs the expression built in lines 31 through 33. This is the or operation between the expressions in line 31 and 32. and this is totally possible with blocking assignments. Notice that the blocking assignment operator is the equal character. Blocking means that any further line of code will be evaluated after this line is evaluated. It has no particular effect on timing. It simply means that the expressions are built in the sequence of the code. I want to be clear on this so I'll say it once more. The order of the lines of code is not the order of the signal changes in time. It's only showing the trajectory of the signals in the circuit. Time is not blocked. The compiler is. Conversely, non-blocking means that…

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